#include "hal_rc8088.h"
#include "hal_Delay.h"
#include <stdlib.h>
#include "userProfileLut.h"
#include "bsp_spi.h"

#ifndef CRC_HW
#include "hal_crc_sw.h"
#endif


/**
 * @Breif  : HAL_RC8088_MemAddrOver   : RC8088 judage Memory Address function
 *
 * @param  : u16MemAddr            : RC8088 memory address
 * @Param  : u16Len                : Read or Write data length 
 *
 * @Returns: RC8088_OperateStatus  : RW_LEN_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_MemAddrOver(uint16_t u16MemAddr, uint16_t u16Len)
{
	if((u16MemAddr>=RC8088_IBUFF0_CP) && (u16MemAddr<=RC8088_IBUFF0_END))
	{
		if((u16MemAddr + u16Len) > RC8088_IBUFF0_END+1)
			return RW_LEN_ERR;
	}
	if((u16MemAddr>=RC8088_IBUFF1_CP) && (u16MemAddr<=RC8088_IBUFF1_END))
	{
		if((u16MemAddr + u16Len) > RC8088_IBUFF1_END+1)
			return RW_LEN_ERR;
	}
	if((u16MemAddr>=RC8088_PBUFF0_BASE) && (u16MemAddr<=RC8088_PBUFF0_END))
	{
		if((u16MemAddr + u16Len) > RC8088_PBUFF0_END+1)
			return RW_LEN_ERR;
	}
	if((u16MemAddr>=RC8088_PBUFF1_BASE) && (u16MemAddr<=RC8088_PBUFF1_END))
	{
		if((u16MemAddr + u16Len) > RC8088_PBUFF1_END+1)
			return RW_LEN_ERR;
	}
	if((u16MemAddr>=RC8088_DBUFF0_BASE) && (u16MemAddr<=RC8088_DBUFF_END))
	{
		if((u16MemAddr + u16Len) > RC8088_DBUFF_END+1)
			return RW_LEN_ERR;
	}
	if((u16MemAddr>=RC8088_CBUFF_BASE) && (u16MemAddr<=RC8088_CBUFF_END))
	{
		if((u16MemAddr + u16Len) > RC8088_CBUFF_END+1)
			return RW_LEN_ERR;
	}
	if((u16MemAddr>=RC8088_TXBUFF_BASE) && (u16MemAddr<=RC8088_TXBUFF_END))
	{
		if((u16MemAddr + u16Len) > RC8088_TXBUFF_END+1)
			return RW_LEN_ERR;
	}
	if((u16MemAddr>=RC8088_FBUFF0_BASE) && (u16MemAddr<=RC8088_FBUFF_END))
	{
		if((u16MemAddr + u16Len) > RC8088_FBUFF_END+1)
			return RW_LEN_ERR;
	}
	if((u16MemAddr>=RC8088_WBUFF_BASE) && (u16MemAddr<=RC8088_WBUFF_END))
	{
		if((u16MemAddr + u16Len) > RC8088_WBUFF_END+1)
			return RW_LEN_ERR;
	}
	return RW_OK;
}


/**
 * @Breif  : HAL_RC8088_GetCrcEsr  : RC8088 Get Crc Error Status function
 *
 * @param  : *pRC8088_RW_Cfg       : pointer to RC8088 read and write configuration
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_CRC_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_GetCrcEsr(RC8088_RWCfg_st *pCfg)
{
	uint8_t u8CrcBuf[2];
	uint8_t u8CmdBuf[5];
	RC8088_RegDat_st CrcSta[1];

	u8CmdBuf[0] = RC8088_READ_REG_SPI_CRC;	
	u8CmdBuf[1] = (uint8_t)((RC8088_REG_LEN >> 10) & 0xFF);
	u8CmdBuf[2] = (uint8_t)((RC8088_REG_LEN >> 2) & 0xFF);
	u8CmdBuf[3] = (uint8_t)((RC8088_ESR0_ADDR >> 8) & 0xFF);
	u8CmdBuf[4] = (uint8_t)(RC8088_ESR0_ADDR & 0xFF);

	if(pCfg->IFMOD == RC8088_SPI_MODE)
	{
		spi_read_transfer_crc(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8CmdBuf,5,CrcSta[0].DATA8, RC8088_REG_LEN,u8CrcBuf);
	}
//	printf("CrcSta[0].DATA32:0x%.8x\n",CrcSta[0].DATA32);
	if(CrcSta[0].DATA32 & RC8088_SPI_CRC_ERR_Msk){
		printf("HAL_RC8088_GetCrcEsr :err crcsta!\n");
		return RW_CRC_ERR;
	}
	return RW_OK;
}

/**
 * @Breif  : HAL_RC8088_CrcCalculate : RC8088 Interface Initiation function
 *
 * make
 * @param  : *pu8CmdBuf            : pointer to command buffer calculated 
 * @param  : u8CmdLen              : calculate command length
 * @param  : *pu8Data              : pointer to data buffer calculated
 * @param  : u16DataLen            : calculate data length
 * @Returns: uint16_t              : CRC Result
 *
 */
uint16_t HAL_RC8088_CrcCalculate(uint8_t *pu8CmdBuf, uint8_t u8CmdLen, uint8_t *pu8Data, uint16_t u16DataLen)
{
	uint16_t u16CrcResult = 0;
	#ifdef CRC_HW
	CRC_CLK_ENABLE;
	CRC_Calculate_Enhence(0xFFFF, CRC_INV_ENABLE, pu8CmdBuf, u8CmdLen, 1);//0xFFFF
	u16CrcResult = CRC_Calculate_Enhence(0xFFFF, CRC_INV_ENABLE, pu8Data, u16DataLen, 0);//0xFFFF
	CRC_CLK_DISABLE;
	#else
	// u16CrcResult = CRC_Calculate_SW(0xFFFF, pu8CmdBuf,u8CmdLen, pu8Data, u16DataLen);
	u16CrcResult = CRC_Calculate_SW(0xFFFF, CRC_INV_DISABLE, pu8CmdBuf,u8CmdLen);
	u16CrcResult = CRC_Calculate_SW(u16CrcResult, CRC_INV_ENABLE, pu8Data, u16DataLen);
	#endif
	return u16CrcResult;
	
}


/**
 * @Breif  : HAL_RC8088_RdReg  : RC8088 Read Register function
 *
 * @param  : *pu8CmdBuf            : pointer to command buffer calculated 
 * @param  : u8CmdLen              : calculate command length
 * @param  : *pu8Data              : pointer to data buffer calculated
 * @param  : u16DataLen            : calculate data length
 * @param  : pu8RdCrc              : pointer to crc from interface
 *
 * @Returns: RC8088_OperateStatus  : RW_CRC_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_CrcCheck(uint8_t *pu8CmdBuf, uint8_t u8CmdLen, uint8_t *pu8Data, uint16_t u16DataLen, uint8_t *pu8RdCrc)
{
	uint16_t u16RdCrc = 0;
	u16RdCrc = ((*(pu8RdCrc+1)) << 8) | (*pu8RdCrc);
//	printf("calc crc:0x%.4x,read crc 0x%.4x\n",HAL_RC8088_CrcCalculate(pu8CmdBuf, u8CmdLen, pu8Data, u16DataLen),u16RdCrc);
	if(u16RdCrc == HAL_RC8088_CrcCalculate(pu8CmdBuf, u8CmdLen, pu8Data, u16DataLen)){
		return RW_OK;
	}
	return RW_CRC_ERR;
}	


/**
 * @Breif  : HAL_RC8088_ClrAll  : RC8088 Clear All function
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_ClrAll(RC8088_RWCfg_st *pCfg)
{
	uint8_t u8WrCmd[3] = {0x81, 0xF9, 0x65};
	
	if(spi_write_transfer(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8WrCmd, 3, u8WrCmd, 0) == 0)
		return RW_OK;
	return RW_IF_ERR;
}
/**
 * @Breif  : HAL_RC8088_ClrAllStatus  : RC8088 Clear All function
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_ClrAllStatus(RC8088_RWCfg_st *pCfg)
{
	RC8088_OperateStatus rtn=RW_OK;
	rtn+=HAL_RC8088_ClrWgen(pCfg);
//	rtn+=HAL_RC8088_ClrMipi();
	rtn+=HAL_RC8088_ClrEdma(pCfg);
	rtn+=HAL_RC8088_ClrFFT (pCfg);
	rtn+=HAL_RC8088_ClrPrep(pCfg);
	return rtn;
}

/**
 * @Breif  : HAL_RC8088_ClrWgen  : RC8088 Clear Wave Generate function
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_ClrWgen(RC8088_RWCfg_st *pCfg)
{
	uint8_t u8WrCmd[3] = {0x82, 0x62, 0x57};
	if(spi_write_transfer(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8WrCmd, 3, u8WrCmd, 0) == 0)
		return RW_OK;
	return RW_IF_ERR;	
}


/**
 * @Breif  : HAL_RC8088_ClrMipi  : RC8088 Clear Mipi function
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_ClrMipi(RC8088_RWCfg_st *pCfg)
{
	uint8_t u8WrCmd[3] = {0x83, 0xEB, 0x46};
	if(spi_write_transfer(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8WrCmd, 3, u8WrCmd, 0) == 0)
		return RW_OK;
	return RW_IF_ERR;
}


/**
 * @Breif  : HAL_RC8088_ClrEdma  : RC8088 Clear Edma function
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_ClrEdma(RC8088_RWCfg_st *pCfg)
{
	uint8_t u8WrCmd[3] = {0x84, 0x54, 0x32};
	if(spi_write_transfer(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8WrCmd, 3, u8WrCmd, 0) == 0)
		return RW_OK;
	return RW_IF_ERR;
}


/**
 * @Breif  : HAL_RC8088_ClrFFT  : RC8088 Clear FFT function
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_ClrFFT(RC8088_RWCfg_st *pCfg)
{
	uint8_t u8WrCmd[3] = {0x85, 0xDD, 0x23};
	if(spi_write_transfer(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8WrCmd, 3, u8WrCmd, 0) == 0)
		return RW_OK;
	return RW_IF_ERR;
}


/**
 * @Breif  : HAL_RC8088_ClrPrep  : RC8088 Clear Prepare function
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_ClrPrep(RC8088_RWCfg_st *pCfg)
{
	uint8_t u8WrCmd[3] = {0x86, 0x46, 0x11};
	if(spi_write_transfer(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8WrCmd, 3, u8WrCmd, 0) == 0)
		return RW_OK;
	return RW_IF_ERR;
}


/**
 * @Breif  : HAL_RC8088_ClrReg  : RC8088 Clear Register function
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_ClrReg(RC8088_RWCfg_st *pCfg)
{
	uint8_t u8WrCmd[3] = {0x87, 0xCF, 0x00};
	if(spi_write_transfer(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8WrCmd, 3, u8WrCmd, 0) == 0)
		return RW_OK;
	return RW_IF_ERR;
}


/**
 * @Breif  : HAL_RC8088_ClrReg  : RC8088 Clear Memory function
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_ClrMem(RC8088_RWCfg_st *pCfg)
{
	uint8_t u8WrCmd[3] = {0x88, 0x38, 0xF8};
	if(spi_write_transfer(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8WrCmd, 3, u8WrCmd, 0) == 0)
		return RW_OK;
	return RW_IF_ERR;
}


/**
 * @Breif  : HAL_RC8088_TrigP10  : RC8088 Triger P10 Model function
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_TrigP10(RC8088_RWCfg_st *pCfg)
{
	uint8_t u8WrCmd[3] = {0x90, 0xF1, 0x64};
	if(spi_write_transfer(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8WrCmd, 3, u8WrCmd, 0) == 0)
		return RW_OK;
	return RW_IF_ERR;
}


/**
 * @Breif  : HAL_RC8088_TrigEdma  : RC8088 Triger Edma Model function
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_TrigEdma(RC8088_RWCfg_st *pCfg)
{
	uint8_t u8WrCmd[3] = {0x91, 0x78, 0x75};
	if(spi_write_transfer(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8WrCmd, 3, u8WrCmd, 0) == 0)
		return RW_OK;
	return RW_IF_ERR;
}


/**
 * @Breif  : HAL_RC8088_RegCrcCheck  : RC8088 Start Register Crc Check function
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_RegCrcCheck(RC8088_RWCfg_st *pCfg)
{
	uint8_t u8WrCmd[3] = {0xA0, 0x72, 0x55};
	if(spi_write_transfer(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8WrCmd, 3, u8WrCmd, 0) == 0)
		return RW_OK;
	return RW_IF_ERR;
}


/**
 * @Breif  : HAL_RC8088_WaveStart  : RC8088 Start Generate Wave function
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_WaveStart(RC8088_RWCfg_st *pCfg)
{
	uint8_t u8WrCmd[3] = {0xA1, 0xFB, 0x44};
	HAL_RC8088_ClrAllStatus(pCfg);
	if(spi_write_transfer(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8WrCmd, 3, u8WrCmd, 0) == 0)
		return RW_OK;
	return RW_IF_ERR;
}


/**
 * @Breif  : HAL_RC8088_WaveStop  : RC8088 Stop Generate Wave function
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_WaveStop(RC8088_RWCfg_st *pCfg)
{
	uint8_t u8WrCmd[3] = {0xA2, 0x60, 0x76};
	if(spi_write_transfer(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8WrCmd, 3, u8WrCmd, 0) == 0)
		return RW_OK;
	return RW_IF_ERR;
}


/**
 * @Breif  : HAL_RC8088_BigEndian  : RC8088 Switch Big Endian Read or Writer Mode function
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_BigEndian(RC8088_RWCfg_st *pCfg)
{
	uint8_t u8WrCmd[3] = {0xB0, 0xF3, 0x45};
	if(spi_write_transfer(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8WrCmd, 3, u8WrCmd, 0) == 0)
		return RW_OK;
	return RW_IF_ERR;
}


/**
 * @Breif  : HAL_RC8088_LittleEndian  : RC8088 Switch Little Endian Read and Writer Mode function
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_LittleEndian(RC8088_RWCfg_st *pCfg)
{
	uint8_t u8WrCmd[3] = {0xB1, 0x7A, 0x54};
	if(spi_write_transfer(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8WrCmd, 3, u8WrCmd, 0) == 0)
		return RW_OK;
	return RW_IF_ERR;
}


/**
 * @Breif  : HAL_RC8088_Init  : RC8088 Switch Little Endian Read or Writer Mode function
 *
 * @param  : *pRC8088_RW_Cfg       : pointer to RC8088 read and write configuration
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_Init(RC8088_RWCfg_st *pRC8088_RW_Cfg)
{
//	BSP_RC8088_InitChipenGPIO();
//	BSP_RC8088_InitInterFace();
	if(pRC8088_RW_Cfg->ENDIAN == RC8088_L_END)
		return HAL_RC8088_LittleEndian(pRC8088_RW_Cfg);
	if(pRC8088_RW_Cfg->ENDIAN == RC8088_B_END)
		return HAL_RC8088_BigEndian(pRC8088_RW_Cfg);
	
	return RW_OK;
}

/**
 * @Breif  : HAL_RC8088_RdReg  : RC8088 Read Register function
 *
 * @param  : *pCfg                 : pointer to RC8088 read and write configuration
 * @param  : *pRegAddr             : RC8088 register address
 * @param  : *pu32ReadRegData      : pointer to read data buffer
 * @param  : u16Len                : read data length
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_LEN_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_RdReg(RC8088_RWCfg_st *pCfg, uint16_t pRegAddr, RC8088_RegDat_st *pu32ReadRegData, uint16_t u16Len)
{
	uint8_t u8Sta = RW_IF_ERR;
	uint16_t u16RegAddr = pRegAddr;
	uint16_t u16ByteLen = 0;
	u16ByteLen = u16Len * 4;
	uint8_t u8CmdBuf[5];
	uint8_t u8CrcBuf[2];
	if(u16RegAddr/4 + u16Len > 0x99)
		return RW_LEN_ERR;

	u8CmdBuf[1] = u16Len >> 8;
	u8CmdBuf[2] = u16Len;
	u8CmdBuf[3] = u16RegAddr >> 8;
	u8CmdBuf[4] = u16RegAddr;

	if(pCfg->IFMOD == RC8088_SPI_MODE)
	{
			u8CmdBuf[0] = RC8088_READ_REG_SPI_CRC;
			u8Sta = spi_read_transfer_crc(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8CmdBuf, 5, pu32ReadRegData->DATA8, (uint32_t)u16ByteLen, u8CrcBuf);
//			printf("data:%.8x,crc:0x%.4x\n",pu32ReadRegData->DATA32,((*(u8CrcBuf+1)) << 8) | (*u8CrcBuf));
			if(HAL_RC8088_CrcCheck(u8CmdBuf, 5, pu32ReadRegData->DATA8, u16ByteLen, u8CrcBuf) == RW_CRC_ERR)
				return RW_CRC_ERR;
	}

	if(u8Sta == 0)
		return RW_OK;
	return RW_IF_ERR;
}


/**
 * @Breif  : HAL_RC8088_RdMem  : RC8088 Read memory function
 *
 * @param  : *pCfg                 : pointer to RC8088 read and write configuration
 * @param  : u16MemAddr            : RC8088 memory address
 * @param  : *pReadMemData         : pointer to read data buffer
 * @param  : u16Len                : read data length
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_LEN_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_RdMem(RC8088_RWCfg_st *pCfg, uint16_t u16MemAddr, RC8088_MemDat_st *pReadMemData, uint16_t u16Len)
{
	if(HAL_RC8088_MemAddrOver(u16MemAddr, u16Len))
		return RW_LEN_ERR;
	uint8_t u8Sta = RW_IF_ERR;
	uint16_t u16ByteLen = 0;
	u16ByteLen = u16Len * 16;
	uint8_t u8CmdBuf[9];
	uint8_t u8CrcBuf[2];
	u8CmdBuf[1] = u16Len >> 8;
	u8CmdBuf[2] = u16Len;
	u8CmdBuf[3] = u16MemAddr >> 8;
	u8CmdBuf[4] = u16MemAddr;
	for(uint8_t i=0; i<4; i++)
		u8CmdBuf[5+i] = 0xFF;
	
	if(pCfg->IFMOD == RC8088_SPI_MODE)
	{
			u8CmdBuf[0] = RC8088_READ_MEM_SPI_CRC;
			u8Sta = spi_read_transfer_crc(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8CmdBuf, 6, pReadMemData->DATA8, (uint32_t)u16ByteLen, u8CrcBuf);
			if(HAL_RC8088_CrcCheck(u8CmdBuf, 6, pReadMemData->DATA8, u16ByteLen, u8CrcBuf) == RW_CRC_ERR)
				return RW_CRC_ERR;
	}

	if(u8Sta == 0)
		return RW_OK;
	return RW_IF_ERR;
}


/**
 * @Breif  : HAL_RC8088_WrReg  : RC8088 Write Register function
 *
 * @param  : *pCfg                 : pointer to RC8088 read and write configuration
 * @param  : *pRegAddr             : RC8088 register address
 * @param  : u16Len                : write data length
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_LEN_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_WrReg(RC8088_RWCfg_st *pCfg, uint16_t pRegAddr,void *pRegDat, uint16_t u16Len)
{
	uint8_t u8Sta = RW_IF_ERR;
	uint16_t u16RegAddr = pRegAddr;
	uint16_t u16ByteLen = 0;
	RC8088_RegDat_st *pWriteRegData = (RC8088_RegDat_st *)pRegDat;
	u16ByteLen = u16Len * 4;
	if(u16RegAddr/4 + u16Len > 0x99){
		return RW_LEN_ERR;
	}
	uint8_t u8CmdBuf[5];
	uint16_t u16CrcBuf[1];
	u8CmdBuf[1] = u16Len >> 8;
	u8CmdBuf[2] = u16Len;
	u8CmdBuf[3] = u16RegAddr >> 8;
	u8CmdBuf[4] = u16RegAddr;

//	printf("pCfg->IFMOD:%d:%d\n",pCfg->IFMOD,RC8088_SPI_MODE);
	if(pCfg->IFMOD == RC8088_SPI_MODE)
	{
			u8CmdBuf[0] = RC8088_Write_REG_SPI_CRC;
			u16CrcBuf[0] = HAL_RC8088_CrcCalculate(u8CmdBuf, 5, pWriteRegData->DATA8, u16ByteLen);
			u8Sta = spi_write_transfer_crc(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8CmdBuf, 5, pWriteRegData->DATA8, (uint32_t)u16ByteLen, (uint8_t *)u16CrcBuf);
//			printf("u16CrcBuf:0x%.8x\n",u16CrcBuf[0]);
			if(HAL_RC8088_GetCrcEsr(pCfg) == 1){
//				printf("crc err!\n");
				return RW_CRC_ERR;
			}

	}
	if(u8Sta == 0)
		return RW_OK;
	return RW_IF_ERR;
}


/**
 * @Breif  : HAL_RC8088_WrMem  : RC8088 Write memory function
 *
 * @param  : *pCfg                 : pointer to RC8088 read and write configuration
 * @param  : u16MemAddr            : RC8088 memory address
 * @param  : *pReadMemData         : pointer to write data buffer
 * @param  : u16Len                : write data length
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_LEN_ERR
 *                                 : RW_OK
 */
// uint8_t a[8192] = {39,7,0,0,0,0,0,0,0,0,0,0,255,255,255,15,255,255,255,15,245,102,89,6,0,192,1,0,36,73,146,236,0,0,0,0,128,106,0,0,0,0,0,0,0,21,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,240,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,22,0,0,0,0,0,0,0,0,0,0,104,22,0,0,0,0,0,0,124,22,0,0,0,0,0,0,124,30,0,0,0,0,0,0,144,30,0,0,0,0,0,0,164,30,0,0,0,0,0,0,184,30,0,0,0,0,0,0,204,30,0,0,0,0,0,0,224,30,0,0,0,0,0,0,244,30,0,0,0,0,0,0,8,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,37,7,0,0,0,0,0,0,0,0,0,0,255,255,255,15,255,255,255,15,245,102,89,6,0,192,1,0,36,73,146,236,0,0,0,0,128,106,0,0,0,0,0,0,12,21,0,0,127,5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,240,21,0,0,5,127,0,0,0,0,0,0,0,0,0,0,64,22,0,0,0,0,0,0,0,0,0,0,104,22,0,0,0,0,0,0,124,22,0,0,0,0,0,0,124,30,1,0,11,0,0,0,144,30,1,0,11,0,0,0,164,30,1,0,11,0,0,0,184,30,1,0,11,0,0,0,204,30,1,0,11,0,0,0,224,30,1,0,11,0,0,0,244,30,1,0,11,0,0,0,8,31,1,0,11,0,0,0,0,0,0,0,0,0,0,0,37,7,0,0,0,0,0,0,0,0,0,0,255,255,255,15,255,255,255,15,245,102,89,6,0,192,1,0,36,73,146,236,0,0,0,0,128,106,0,0,0,0,0,0,12,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,240,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,22,0,0,0,0,0,0,0,0,0,0,104,22,0,0,0,0,0,0,124,22,0,0,0,0,0,0,125,30,0,0,0,0,0,0,145,30,0,0,0,0,0,0,165,30,0,0,0,0,0,0,185,30,0,0,0,0,0,0,205,30,0,0,0,0,0,0,225,30,0,0,0,0,0,0,245,30,0,0,0,0,0,0,9,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,37,7,0,0,0,0,0,0,0,0,0,0,255,255,255,15,255,255,255,15,245,102,89,6,0,192,1,0,36,73,146,236,0,0,0,0,128,106,0,0,0,0,0,0,12,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,240,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,22,0,0,0,0,0,0,0,0,0,0,104,22,0,0,0,0,0,0,124,22,0,0,0,0,0,0,126,30,0,0,0,0,0,0,146,30,0,0,0,0,0,0,166,30,0,0,0,0,0,0,186,30,0,0,0,0,0,0,206,30,0,0,0,0,0,0,226,30,0,0,0,0,0,0,246,30,0,0,0,0,0,0,10,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,37,7,0,0,0,0,0,0,0,0,0,0,255,255,255,15,255,255,255,15,245,102,89,6,0,192,1,0,36,73,146,236,0,0,0,0,128,106,0,0,0,0,0,0,12,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,240,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,22,0,0,0,0,0,0,0,0,0,0,104,22,0,0,0,0,0,0,124,22,0,0,0,0,0,0,127,30,0,0,0,0,0,0,147,30,0,0,0,0,0,0,167,30,0,0,0,0,0,0,187,30,0,0,0,0,0,0,207,30,0,0,0,0,0,0,227,30,0,0,0,0,0,0,247,30,0,0,0,0,0,0,11,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,37,7,0,0,0,0,0,0,0,0,0,0,255,255,255,15,255,255,255,15,245,102,89,6,0,192,1,0,36,73,146,236,0,0,0,0,128,106,0,0,0,0,0,0,12,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,240,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,22,0,0,0,0,0,0,0,0,0,0,104,22,0,0,0,0,0,0,124,22,0,0,0,0,0,0,128,30,0,0,0,0,0,0,148,30,0,0,0,0,0,0,168,30,0,0,0,0,0,0,188,30,0,0,0,0,0,0,208,30,0,0,0,0,0,0,228,30,0,0,0,0,0,0,248,30,0,0,0,0,0,0,12,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,37,7,0,0,0,0,0,0,0,0,0,0,255,255,255,15,255,255,255,15,245,102,89,6,0,192,1,0,36,73,146,236,0,0,0,0,128,106,0,0,0,0,0,0,12,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,240,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,22,0,0,0,0,0,0,0,0,0,0,104,22,0,0,0,0,0,0,124,22,0,0,0,0,0,0,129,30,0,0,0,0,0,0,149,30,0,0,0,0,0,0,169,30,0,0,0,0,0,0,189,30,0,0,0,0,0,0,209,30,0,0,0,0,0,0,229,30,0,0,0,0,0,0,249,30,0,0,0,0,0,0,13,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,37,7,0,0,0,0,0,0,0,0,0,0,255,255,255,15,255,255,255,15,245,102,89,6,0,192,1,0,36,73,146,236,0,0,0,0,128,106,0,0,0,0,0,0,12,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,240,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,22,0,0,0,0,0,0,0,0,0,0,104,22,0,0,0,0,0,0,124,22,0,0,0,0,0,0,130,30,0,0,0,0,0,0,150,30,0,0,0,0,0,0,170,30,0,0,0,0,0,0,190,30,0,0,0,0,0,0,210,30,0,0,0,0,0,0,230,30,0,0,0,0,0,0,250,30,0,0,0,0,0,0,14,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,37,7,0,0,0,0,0,0,0,0,0,0,255,255,255,15,255,255,255,15,245,102,89,6,0,192,1,0,36,73,146,236,0,0,0,0,128,106,0,0,0,0,0,0,12,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,240,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,22,0,0,0,0,0,0,0,0,0,0,104,22,0,0,0,0,0,0,124,22,0,0,0,0,0,0,131,30,0,0,0,0,0,0,151,30,0,0,0,0,0,0,171,30,0,0,0,0,0,0,191,30,0,0,0,0,0,0,211,30,0,0,0,0,0,0,231,30,0,0,0,0,0,0,251,30,0,0,0,0,0,0,15,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,37,7,0,0,0,0,0,0,0,0,0,0,255,255,255,15,255,255,255,15,245,102,89,6,0,192,1,0,36,73,146,236,0,0,0,0,128,106,0,0,0,0,0,0,12,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,240,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,22,0,0,0,0,0,0,0,0,0,0,104,22,0,0,0,0,0,0,124,22,0,0,0,0,0,0,132,30,0,0,0,0,0,0,152,30,0,0,0,0,0,0,172,30,0,0,0,0,0,0,192,30,0,0,0,0,0,0,212,30,0,0,0,0,0,0,232,30,0,0,0,0,0,0,252,30,0,0,0,0,0,0,16,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,37,7,0,0,0,0,0,0,0,0,0,0,255,255,255,15,255,255,255,15,245,102,89,6,0,192,1,0,36,73,146,236,0,0,0,0,128,106,0,0,0,0,0,0,12,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,240,21,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,22,0,0,0,0,0,0,0,0,0,0,104,22,0,0,0,0,0,0,124,22,0,0,0,0,0,0,133,30,0,0,0,0,0,0,153,30,0,0,0,0,0,0,173,30,0,0,0,0,0,0,193,30,0,0,0,0,0,0,213,30,0,0,0,0,0,0,233,30,0,0,0,0,0,0,253,30,0,0,0,0,0,0,17,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,37,7,0,0,0,0,0,0,0,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RC8088_OperateStatus HAL_RC8088_WrMem(RC8088_RWCfg_st *pCfg, uint16_t u16MemAddr, RC8088_MemDat_st *pWriteMemData, uint16_t u16Len)
{
	if(HAL_RC8088_MemAddrOver(u16MemAddr, u16Len))
		return RW_LEN_ERR;
	uint8_t u8Sta = RW_IF_ERR;
	uint16_t u16CrcBuf[1];
	uint16_t u16ByteLen = 0;
	u16ByteLen = u16Len * 16;
	uint8_t u8CmdBuf[5];
	u8CmdBuf[1] = u16Len >> 8;
	u8CmdBuf[2] = u16Len;
	u8CmdBuf[3] = u16MemAddr >> 8;
	u8CmdBuf[4] = u16MemAddr;
	if(pCfg->IFMOD == RC8088_SPI_MODE)
	{
			u8CmdBuf[0] = RC8088_Write_MEM_SPI_CRC;
			u16CrcBuf[0] = HAL_RC8088_CrcCalculate(u8CmdBuf, 5, pWriteMemData->DATA8, u16ByteLen);
#if	0
			printf("u8CmdBuf :");
			for(uint32_t i = 0; i < 5; i++)
			{
				printf("%u ", u8CmdBuf[i]);
			}
			printf("\n");
			printf("pWriteMemData->DATA8 :");
			for(uint32_t j = 0; j < u16ByteLen; j++)
			{
				printf("%u ", pWriteMemData->DATA8[j]);
			}
			printf("\n");
#endif
			u8Sta = spi_write_transfer_crc(g_spi_dev_info.dev_info[pCfg->SPI_RF_DEV].fd, u8CmdBuf, 5, pWriteMemData->DATA8, (uint32_t)u16ByteLen, (uint8_t *)u16CrcBuf);
			if(HAL_RC8088_GetCrcEsr(pCfg) == 1)
				return RW_CRC_ERR;
	}

	if(u8Sta == 0)
		return RW_OK;
	return RW_IF_ERR;
}



/**
 * @Breif  : HAL_RC8088_GetInt  : RC8088 Get Interupt flag function
 *
 * @param  : *pCfg                 : pointer to RC8088 read and write configuration
 * @param  : *pRegAddr          : RC8088 register address
 *
 * @Returns: RC8088_OperateStatus  : Interupt flag status
 *
 */
uint32_t HAL_RC8088_GetInt(RC8088_RWCfg_st *pCfg, uint16_t pRegAddr)
{
	RC8088_RegDat_st u32Sta[1];
	HAL_RC8088_RdReg(pCfg, pRegAddr, u32Sta, 1);
	
	return u32Sta[0].DATA32;
}


/**
 * @Breif  : HAL_RC8088_ClrAllInt  : RC8088 Clear All Interupt flag function
 *
 * @param  : *pCfg                 : pointer to RC8088 read and write configuration
 * @param  : *pRegAddr             : RC8088 register address
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_LEN_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_ClrAllInt(RC8088_RWCfg_st *pCfg, RC8088_INT_st *pRegAddr)
{
	pRegAddr->ISR.WORD = 0xFFFFFFFF;
	pRegAddr->ESR0.WORD = 0xFFFFFFFF;
	pRegAddr->ESR1.WORD = 0xFFFFFFFF;
	return HAL_RC8088_WrReg(pCfg, REG_ISR, &pRegAddr->ISR, 3);
}
/**
 * @Breif  : HAL_RC8088_ClrESR0  : RC8088 Clear ESR0 flag function
 *
 * @param  : *pCfg                 : pointer to RC8088 read and write configuration
 * @param  : *pRegAddr             : RC8088 register address
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_LEN_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_ClrESR0Int(RC8088_RWCfg_st *pCfg, RC8088_INT_st *pRegAddr)
{
	pRegAddr->ESR0.WORD = 0xFFFFFFFF;
	return HAL_RC8088_WrReg(pCfg, REG_ESR0, &pRegAddr->ESR0, 1);
}

/**
 * @Breif  : HAL_RC8088_ClrESR1  : RC8088 Clear All ESR1 flag function
 *
 * @param  : *pCfg                 : pointer to RC8088 read and write configuration
 * @param  : *pRegAddr             : RC8088 register address
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_LEN_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_ClrESR1Int(RC8088_RWCfg_st *pCfg, RC8088_INT_st *pRegAddr)
{
	pRegAddr->ESR1.WORD = 0xFFFFFFFF;
	return HAL_RC8088_WrReg(pCfg, REG_ESR1, &pRegAddr->ESR1, 1);
}

/**
 * @Breif  : HAL_RC8088_CaliberADC : RC8088 Caliber ADC function
 *
 * @param  : *pCfg                 : pointer to RC8088 read and write configuration
 * @param  : *pRegAddr             : RC8088 register address
 * @param  : u8Channel             : Caliber ADC Channel
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_LEN_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_CaliberADC(RC8088_RWCfg_st *pCfg, RC8088_ANA_st *pRegAddr, uint8_t u8Channel)
{
	uint32_t u8TestNum[16] = {0x7,0x6,0x5,0x4,0x3,0x2,0x1,0x0,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF};
	uint32_t u32TempValue[6] = {0};
	RC8088_RegDat_st u32Rdata[26]={0};
	
    pRegAddr->CFG00.BIT.enrxbb = 0; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG00, &pRegAddr->CFG00, 1);  //switch rxbb
    
    
	pRegAddr->CFG12.WORD = (pRegAddr->CFG12.WORD&0xFFFFFF00)|u8Channel; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG12, &pRegAddr->CFG12, 1);  //����ADC ͨ��1 caliber
	pRegAddr->CFG14.WORD = 0x00007770; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
	pRegAddr->CFG14.WORD = 0x00017770; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);

	for(uint8_t j = 1;j<4;j++)
	{
		uint8_t calibStatus = 0;
		for(uint8_t i = 1;i<16;i++)
		{
			HAL_RC8088_RdReg(pCfg, REG_ANA_STA1, u32Rdata+1, 1);
			if((u32Rdata[1].DATA32&(0x1<<(j-1))) == 0)
			{
				calibStatus = 1;
				u32TempValue[0] &= ~(0xF<<4*j);
				u32TempValue[0] |= (u8TestNum[i-1]<<4*j);  //���� [7:4]Ϊ����
				break;
			}
			if((u32Rdata[1].DATA32&(0x1<<(j-1))) != 0)
			{
				pRegAddr->CFG14.WORD &= ~(0xF<<4*j);
				pRegAddr->CFG14.WORD |= (u8TestNum[i]<<4*j);    //�öν�����һ��
			
				pRegAddr->CFG14.WORD &= ~(0xF<<16);   //����bit16
				HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
				pRegAddr->CFG14.WORD |= (0x1<<16);   //bit16=1  ��λ����������
				HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
			}
		}
		if(calibStatus==0){
			u32TempValue[0] &= ~(0xF<<4*j);
			u32TempValue[0] |= (0xF<<4*j);  
		}
	}
	
	//����У׼WGEN_ANA_CFG14<18:16>=001
	pRegAddr->CFG14.WORD = 0x00007777; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
	pRegAddr->CFG14.WORD = 0x00027777; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);

	for(uint8_t j = 3;j<7;j++)
	{
		uint8_t calibStatus = 0;	
		for(uint8_t i = 1;i<16;i++)
		{
			HAL_RC8088_RdReg(pCfg, REG_ANA_STA1, u32Rdata+1, 1);
			if((u32Rdata[1].DATA32&(0x1<<j)) == 0)
			{
				u32TempValue[1] &= ~(0xF<<4*(j-3));
				u32TempValue[1] |= (u8TestNum[i-1]<<4*(j-3));  //���� [7:4]Ϊ����
				break;
			}
			if((u32Rdata[1].DATA32&(0x1<<j)) != 0)
			{
				pRegAddr->CFG14.WORD &= ~(0xF<<4*(j-3));
				pRegAddr->CFG14.WORD |= (u8TestNum[i]<<4*(j-3));    //�öν�����һ��
				pRegAddr->CFG14.WORD &= ~(0xF<<16);   //����bit16
				HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
				pRegAddr->CFG14.WORD |= (0x2<<16);   //bit16=1  ��λ����������
				HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
			}
		}
		if(calibStatus==0){
			u32TempValue[1] &= ~(0xF<<4*(j-3));
			u32TempValue[1] |= (0xF<<4*(j-3));  	
		}
	}

	pRegAddr->CFG14.WORD = 0x00007777; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
	pRegAddr->CFG14.WORD = 0x00037777; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);

	for(uint8_t j = 7;j<11;j++)
	{
		uint8_t calibStatus=0;
		for(uint8_t i = 1;i<16;i++)
		{
			HAL_RC8088_RdReg(pCfg, REG_ANA_STA1, u32Rdata+1, 1);
			if((u32Rdata[1].DATA32&(0x1<<j)) == 0)
			{
				calibStatus=1;
				u32TempValue[2] &= ~(0xF<<4*(j-7));
				u32TempValue[2] |= (u8TestNum[i-1]<<4*(j-7));  //���� [7:4]Ϊ����
				break;
			}
			if((u32Rdata[1].DATA32&(0x1<<j)) != 0)
			{
				pRegAddr->CFG14.WORD &= ~(0xF<<4*(j-7));
				pRegAddr->CFG14.WORD |= (u8TestNum[i]<<4*(j-7));    //�öν�����һ��

				pRegAddr->CFG14.WORD &= ~(0xf<<16);   //����bit16
				HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
				pRegAddr->CFG14.WORD |= (0x3<<16);   //bit16=1  ��λ����������
				HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
			}
		}
		if(calibStatus==0){
			u32TempValue[2] &= ~(0xF<<4*(j-7));
			u32TempValue[2] |= (0xF<<4*(j-7));  	
		}
	}
	
	pRegAddr->CFG14.WORD = 0x00007777; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
	pRegAddr->CFG14.WORD = 0x00047777; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);

	for(uint8_t j = 11;j<15;j++)
	{
		uint8_t calibStatus=0;
		for(uint8_t i = 1;i<16;i++)
		{
			HAL_RC8088_RdReg(pCfg,  REG_ANA_STA1, u32Rdata+1, 1);
			if((u32Rdata[1].DATA32&(0x1<<j)) == 0)
			{
				calibStatus=1;
				u32TempValue[3] &= ~(0xF<<4*(j-11));
				u32TempValue[3] |= (u8TestNum[i-1]<<4*(j-11));  //���� [7:4]Ϊ����
				break;
			}
			if((u32Rdata[1].DATA32&(0x1<<j)) != 0)
			{
				pRegAddr->CFG14.WORD &= ~(0xF<<4*(j-11));
				pRegAddr->CFG14.WORD |= (u8TestNum[i]<<4*(j-11));    //�öν�����һ��
				pRegAddr->CFG14.WORD &= ~(0xf<<16);   //����bit16
				HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
				pRegAddr->CFG14.WORD |= (0x4<<16);   //bit16=1  ��λ����������
				HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
			}
		}
		if(calibStatus==0){
				u32TempValue[3] &= ~(0xF<<4*(j-11));
				u32TempValue[3] |= (0xF<<4*(j-11)); 
		}
	}
	
	pRegAddr->CFG14.WORD = 0x00007777; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
	pRegAddr->CFG14.WORD = 0x00057777; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
	
	for(uint8_t j = 15;j<19;j++)
	{
		uint8_t calibStatus=0;
		for(uint8_t i = 1;i<16;i++)
		{
			HAL_RC8088_RdReg(pCfg, REG_ANA_STA1, u32Rdata+1, 1);
			if((u32Rdata[1].DATA32&(0x1<<j)) == 0)
			{
				calibStatus=1;
				u32TempValue[4] &= ~(0xF<<4*(j-15));
				u32TempValue[4] |= (u8TestNum[i-1]<<4*(j-15));  //���� [7:4]Ϊ����
				break;
			}
			if((u32Rdata[1].DATA32&(0x1<<j)) != 0)
			{
				pRegAddr->CFG14.WORD &= ~(0xF<<4*(j-15));
				pRegAddr->CFG14.WORD |= (u8TestNum[i]<<4*(j-15));    //�öν�����һ��
		
				pRegAddr->CFG14.WORD &= ~(0xf<<16);   //����bit16
				HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
				pRegAddr->CFG14.WORD |= (0x5<<16);   //bit16=1  ��λ����������
				HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
			}
		}
		if(calibStatus==0){
				u32TempValue[4] &= ~(0xF<<4*(j-15));
				u32TempValue[4] |= (0xF<<4*(j-15));  
		}
	}
	
	pRegAddr->CFG14.WORD = 0x00007777; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
	pRegAddr->CFG14.WORD = 0x00067777; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);

	for(uint8_t j = 19;j<21;j++)
	{
		uint8_t calibStatus=0;
		for(uint8_t i = 1;i<16;i++)
		{
			HAL_RC8088_RdReg(pCfg, REG_ANA_STA1, u32Rdata+1, 1);
			if((u32Rdata[1].DATA32&(0x1<<j)) == 0)
			{
				calibStatus=1;
				u32TempValue[5] &= ~(0xF<<4*(j-19));
				u32TempValue[5] |= (u8TestNum[i-1]<<4*(j-19));  //���� [7:4]Ϊ����
				break;
			}
			if((u32Rdata[1].DATA32&(0x1<<j)) != 0)
			{
				pRegAddr->CFG14.WORD &= ~(0xF<<4*(j-19));
				pRegAddr->CFG14.WORD |= (u8TestNum[i]<<4*(j-19));    //�öν�����һ��
				pRegAddr->CFG14.WORD &= ~(0xf<<16);   //����bit16
				HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
				pRegAddr->CFG14.WORD |= (0x6<<16);   //bit16=1  ��λ����������
				HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
			}
		}
		if(calibStatus==0){
				u32TempValue[5] &= ~(0xF<<4*(j-19));
				u32TempValue[5] |= (0xF<<4*(j-19));  
		}
	}

	pRegAddr->CFG12.WORD = (pRegAddr->CFG12.WORD&0xFFFFFF00); HAL_RC8088_WrReg(pCfg,REG_ANA_CFG12, &pRegAddr->CFG12, 1);   //�ر�ofs calibration  en	
	pRegAddr->CFG14.WORD = 0x00010000|u32TempValue[0]; HAL_RC8088_WrReg(pCfg,REG_ANA_CFG14, &pRegAddr->CFG14, 1);
	pRegAddr->CFG12.WORD = (pRegAddr->CFG12.WORD&0xFFFFFF00)|u8Channel; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG12, &pRegAddr->CFG12, 1);   //����ADC ͨ��1 caliber
	
	pRegAddr->CFG12.WORD = (pRegAddr->CFG12.WORD&0xFFFFFF00); HAL_RC8088_WrReg(pCfg, REG_ANA_CFG12, &pRegAddr->CFG12, 1);   //�ر�ofs calibration  en	
	pRegAddr->CFG14.WORD = 0x00020000|u32TempValue[1]; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
	pRegAddr->CFG12.WORD = (pRegAddr->CFG12.WORD&0xFFFFFF00)|u8Channel; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG12, &pRegAddr->CFG12, 1);   //����ADC ͨ��1 caliber
	
	pRegAddr->CFG12.WORD = (pRegAddr->CFG12.WORD&0xFFFFFF00); HAL_RC8088_WrReg(pCfg, REG_ANA_CFG12, &pRegAddr->CFG12, 1);   //�ر�ofs calibration  en	
	pRegAddr->CFG14.WORD = 0x00030000|u32TempValue[2]; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
	pRegAddr->CFG12.WORD = (pRegAddr->CFG12.WORD&0xFFFFFF00)|u8Channel; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG12, &pRegAddr->CFG12, 1);   //����ADC ͨ��1 caliber
	
	pRegAddr->CFG12.WORD = (pRegAddr->CFG12.WORD&0xFFFFFF00); HAL_RC8088_WrReg(pCfg, REG_ANA_CFG12, &pRegAddr->CFG12, 1);   //�ر�ofs calibration  en		
	pRegAddr->CFG14.WORD = 0x00040000|u32TempValue[3]; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
	pRegAddr->CFG12.WORD = (pRegAddr->CFG12.WORD&0xFFFFFF00)|u8Channel; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG12, &pRegAddr->CFG12, 1);   //����ADC ͨ��1 caliber

	pRegAddr->CFG12.WORD = (pRegAddr->CFG12.WORD&0xFFFFFF00); HAL_RC8088_WrReg(pCfg, REG_ANA_CFG12, &pRegAddr->CFG12, 1);   //�ر�ofs calibration  en	
	pRegAddr->CFG14.WORD = 0x00050000|u32TempValue[4]; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
	pRegAddr->CFG12.WORD = (pRegAddr->CFG12.WORD&0xFFFFFF00)|u8Channel; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG12, &pRegAddr->CFG12, 1);   //����ADC ͨ��1 caliber
	
	pRegAddr->CFG12.WORD = (pRegAddr->CFG12.WORD&0xFFFFFF00); HAL_RC8088_WrReg(pCfg, REG_ANA_CFG12, &pRegAddr->CFG12, 1);   //�ر�ofs calibration  en	
	pRegAddr->CFG14.WORD = 0x00060000|u32TempValue[5]; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
	pRegAddr->CFG12.WORD = (pRegAddr->CFG12.WORD&0xFFFFFF00)|u8Channel; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG12, &pRegAddr->CFG12, 1);   //����ADC ͨ��1 caliber
	pRegAddr->CFG12.WORD = (pRegAddr->CFG12.WORD&0xFFFFFF00); HAL_RC8088_WrReg(pCfg, REG_ANA_CFG12, &pRegAddr->CFG12, 1);   //�ر�ofs calibration  en
	pRegAddr->CFG14.WORD = 0x00000000; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);   //�ر�  У׼����
	#if 0
		printf("channel1 RC8088->ANA_STA.STA1= 0x%08x \n",u32TempValue[0]);
		printf("channel2 RC8088->ANA_STA.STA1= 0x%08x \n",u32TempValue[1]);
		printf("channel3 RC8088->ANA_STA.STA1= 0x%08x \n",u32TempValue[2]);	
		printf("channel4 RC8088->ANA_STA.STA1= 0x%08x \n",u32TempValue[3]);	
		printf("channel5 RC8088->ANA_STA.STA1= 0x%08x \n",u32TempValue[4]);	
		printf("channel6 RC8088->ANA_STA.STA1= 0x%08x \n",u32TempValue[5]);
	#endif
	pRegAddr->CFG00.BIT.enrxbb = 0xFF; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG00, &pRegAddr->CFG00, 1);  //switch rxbb
	return HAL_RC8088_WrReg(pCfg, REG_ANA_CFG14, &pRegAddr->CFG14, 1);
}
/**
 * @Breif  : HAL_RC8088_CaliberVCO : RC8088 Caliber VCO function
 *
 * @param  : *pCfg                 : pointer to RC8088 read and write configuration
 * @param  : startFreq             : RC8088 start freq
 * @param  : u8Channel             : Caliber ADC Channel
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_LEN_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_profileManFreqTest(RC8088_RWCfg_st *pCfg, RC8088_RegCfg_st *pRegAddr,uint32_t startFreq)
{
		RC8088_OperateStatus rtn;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG0.BIT.profile_man_vld=1;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG1.BIT.ramp_a_time=10;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG1.BIT.ramp_a_inc=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG2.BIT.ramp_b_time=10;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG2.BIT.ramp_b_inc=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG3.BIT.ramp_c_time=10;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG3.BIT.ramp_c_inc=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG4.BIT.startFreq=startFreq;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG5.BIT.txEn=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG5.BIT.adcRma=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG6.BIT.tx3Phase=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG6.BIT.tx2Phase=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG6.BIT.tx1Phase=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG6.BIT.tx0Phase=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG7.BIT.tx7Phase=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG7.BIT.tx6Phase=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG7.BIT.tx5Phase=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG7.BIT.tx4Phase=0;	
		pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.loopNum=0;	
		pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.loopInf=1;	
		pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.pa_en_maskC=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.pa_en_maskB=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.pa_en_maskA=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.pll_acc_maskC=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.pll_acc_maskB=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.pll_acc_maskA=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.ramp_sycn_maskC=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.ramp_sycn_maskB=0;
		pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.ramp_sycn_maskA=0;
		rtn=HAL_RC8088_WrReg(pCfg, REG_PROF_MAN_CFG0, &pRegAddr->PROFILE_MAN.ProfileMan_CFG0, 9);
		HAL_RC8088_WaveStart(pCfg);
		return rtn;
}
/**
 * @Breif  : HAL_RC8088_CaliberVCO : RC8088 Caliber VCO function
 *
 * @param  : *pCfg                 : pointer to RC8088 read and write configuration
 * @param  : startFreq             : RC8088 start freq
 * @param  : u8Channel             : Caliber ADC Channel
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_LEN_ERR
 *                                 : RW_OK
 */
#define NUM_PLL1_VCOBAND     8
#define NUM_PLL2_VCOBAND_LK  8
#define NUM_PLL2_VCOBAND_HK  4
#define PLL1_VCO_THRES    (0x03)  //ANACFG8 BIT[12:11]: 0x00:V-800   0x03:V-600
static RC8088_OperateStatus PLL1_VCO_Calib(RC8088_RWCfg_st *pCfg, RC8088_RegCfg_st *pRegAddr){
	uint32_t rdata_cfg =0;
	uint32_t reg_sta=0;
	uint8_t pllCnt=0;
	uint8_t pll_Val[NUM_PLL1_VCOBAND]={0};
    pRegAddr->ANA.CFG08.WORD=pRegAddr->ANA.CFG08.WORD&0xFFFF07FF; //old:0xFFFFC7FF
    pRegAddr->ANA.CFG08.WORD=pRegAddr->ANA.CFG08.WORD|(PLL1_VCO_THRES<<11)|(0x02<<14);
    HAL_RC8088_WrReg(pCfg, REG_ANA_CFG08,&pRegAddr->ANA.CFG08, 1);
	HAL_RC8088_RdReg(pCfg,REG_ANA_CFG07, (RC8088_RegDat_st *)&rdata_cfg, 1);
	rdata_cfg &= ~(0x7<<12);   //����[14:12]
    pRegAddr->ANA.CFG02.WORD=pRegAddr->ANA.CFG02.WORD&0xFFFFFFCF;HAL_RC8088_WrReg(pCfg, REG_ANA_CFG02, &pRegAddr->ANA.CFG02, 1); 
	for(uint8_t i = 0;i<NUM_PLL1_VCOBAND;i++)
	{
			pRegAddr->ANA.CFG07.WORD = rdata_cfg|(i<<12); //printf("wdata_cfg[1] = 0x%08x \n",wdata_cfg[1]);
			HAL_RC8088_WrReg(pCfg, REG_ANA_CFG07, &pRegAddr->ANA.CFG07, 1);
			HW_Delay_ms(1);
			HAL_RC8088_ClrESR1Int(pCfg,&pRegAddr->INT);   //���֮ǰ״̬  //00000800
			HW_Delay_ms(1);
			reg_sta = HAL_RC8088_GetInt(pCfg,REG_ESR1); 
			if(((reg_sta &(0x1<<10))== 0)&&((reg_sta & (0x1<<11)) == 0))
			{
                #if 0 //auto
                    pll_Val[pllCnt] = i;
                    pllCnt++;	
                #endif
                #if 1 //manual
                    pRegAddr->ANA.CFG02.WORD=pRegAddr->ANA.CFG02.WORD|(1<<4);HAL_RC8088_WrReg(pCfg, REG_ANA_CFG02, &pRegAddr->ANA.CFG02, 1); 
                    pRegAddr->ANA.CFG02.WORD=pRegAddr->ANA.CFG02.WORD|(3<<4);HAL_RC8088_WrReg(pCfg, REG_ANA_CFG02, &pRegAddr->ANA.CFG02, 1); 
                    reg_sta = HAL_RC8088_GetInt(pCfg,REG_ANA_STA3); 
                    pRegAddr->ANA.CFG02.WORD=pRegAddr->ANA.CFG02.WORD&0xFFFFFFCF;HAL_RC8088_WrReg(pCfg, REG_ANA_CFG02, &pRegAddr->ANA.CFG02, 1); 
                    reg_sta=reg_sta&0x3FF;printf("PLL1:adc=%d \n",reg_sta);
                    if(reg_sta>164){ //adc1:164=250mV
                        pll_Val[pllCnt] = i;
                        pllCnt++;	                
                    }                   
                #endif
			}
	}
    pRegAddr->ANA.CFG08.WORD=pRegAddr->ANA.CFG08.WORD&0xFFFF3FFF; //old:0xFFFFC7FF
    HAL_RC8088_WrReg(pCfg, REG_ANA_CFG08, &pRegAddr->ANA.CFG08, 1);
	if(pllCnt==0){
		pRegAddr->ANA.CFG07.WORD=rdata_cfg;
		printf("PLL1 vcoband calib err:no band\n");
	}else if(pllCnt==1){
		pRegAddr->ANA.CFG07.WORD = rdata_cfg|(pll_Val[0]<<12); 
	}else{
		pRegAddr->ANA.CFG07.WORD = rdata_cfg|(pll_Val[1]<<12); 
	}
	HAL_RC8088_WrReg(pCfg, REG_ANA_CFG07, &pRegAddr->ANA.CFG07, 1);
	printf("PLL1_VCO: CFG07 = 0x%08X\n",pRegAddr->ANA.CFG07.WORD);
	HAL_RC8088_ClrESR1Int(pCfg,&pRegAddr->INT);   //���֮ǰ״̬  //00000800
	reg_sta = HAL_RC8088_GetInt(pCfg,REG_ESR1); 
	if((reg_sta &(0x1<<10))||(reg_sta & (0x1<<11))){
		printf("PLL1 vcoband calib err = 0x%08x\n",reg_sta);
		return RW_RTN_ERR;
	}else{
		return RW_OK;
	}
} 
#define PLL2_VCO_THRES    (0x03)  //ANACFG9 BIT[9:7]: 0x00:V-800   0x03:V-600
static RC8088_OperateStatus PLL2_VCO_Calib(RC8088_RWCfg_st *pCfg, RC8088_RegCfg_st *pRegAddr,uint32_t startFreq,uint32_t stopFreq,uint32_t rdata_cfg){
	RC8088_OperateStatus rtn=RW_OK;
	uint32_t reg_sta = 0;
	uint8_t pll2StartVal[NUM_PLL2_VCOBAND_LK] = {0};
	uint8_t pll2StopVal[NUM_PLL2_VCOBAND_LK] = {0};
	uint8_t pllStartCnt=0;
	uint8_t pllStopCnt=0;
	uint32_t numPLL2Vcoband=0;
    
    pRegAddr->ANA.CFG09.WORD=pRegAddr->ANA.CFG09.WORD&0xFFFFC47F;
    pRegAddr->ANA.CFG09.WORD=pRegAddr->ANA.CFG09.WORD|(PLL2_VCO_THRES<<7)|(6<<11);
    HAL_RC8088_WrReg(pCfg, REG_ANA_CFG09, &pRegAddr->ANA.CFG09, 1);
	if((rdata_cfg&0x00000003) == 1)
	{
		printf("PLL2_VCOband_LK \n");
		numPLL2Vcoband = NUM_PLL2_VCOBAND_LK;
	}else if((rdata_cfg&0x00000003) == 2)
	{
		printf("PLL2_VCOband_HK \n");
		numPLL2Vcoband = NUM_PLL2_VCOBAND_HK;
	}else{
		printf("PLL2_VCOband %08X noLK noHK \n",rdata_cfg);
		return RW_RTN_ERR;
	}
	HAL_RC8088_profileManFreqTest(pCfg,pRegAddr,startFreq);
	rdata_cfg &= ~(0x7<<12);   //����[14:12]
    pRegAddr->ANA.CFG02.WORD=pRegAddr->ANA.CFG02.WORD&0xFFFFFF3F;
	for(uint8_t i = 0;i<numPLL2Vcoband;i++)
	{
			pRegAddr->ANA.CFG01.WORD = rdata_cfg|(i<<12);// printf("wdata_cfg[7] = 0x%08x \n",wdata_cfg[7]);
			HAL_RC8088_WrReg(pCfg, REG_ANA_CFG01, &pRegAddr->ANA.CFG01, 1);
			HW_Delay_ms(1);
			HAL_RC8088_ClrESR1Int(pCfg,&pRegAddr->INT);   //���֮ǰ״̬  //00000800
			HW_Delay_ms(1);
			reg_sta = HAL_RC8088_GetInt(pCfg,REG_ESR1); 
			if(((reg_sta &(0x1<<12))== 0)&&((reg_sta & (0x1<<13)) == 0))
			{
                #if 0 //auto
                    pll2StartVal[pllStartCnt] = i;
                    pllStartCnt++;	
                #endif
                #if 1 //manual
                    pRegAddr->ANA.CFG02.WORD=pRegAddr->ANA.CFG02.WORD|(1<<6);HAL_RC8088_WrReg(pCfg, REG_ANA_CFG02, &pRegAddr->ANA.CFG02, 1); 
                    pRegAddr->ANA.CFG02.WORD=pRegAddr->ANA.CFG02.WORD|(3<<6);HAL_RC8088_WrReg(pCfg, REG_ANA_CFG02, &pRegAddr->ANA.CFG02, 1); 
                    reg_sta = HAL_RC8088_GetInt(pCfg,REG_ANA_STA3); 
                    pRegAddr->ANA.CFG02.WORD=pRegAddr->ANA.CFG02.WORD&0xFFFFFF3F;HAL_RC8088_WrReg(pCfg, REG_ANA_CFG02, &pRegAddr->ANA.CFG02, 1); 
                    reg_sta=(reg_sta>>10)&0x3FF;printf("PLL2:adc=%d \n",reg_sta);
                    if(reg_sta>157){//adc2:157=250mV
                        pll2StartVal[pllStartCnt] = i;
                        pllStartCnt++;	                
                    }
                #endif
			}
	}
	HAL_RC8088_WaveStop(pCfg);
    
	if(pllStartCnt==0){ 
		pRegAddr->ANA.CFG01.WORD = rdata_cfg;
		printf("PLL2 %08X start no band\n",rdata_cfg);
		rtn = RW_RTN_ERR;
	}else{              //stopFreq 
		HAL_RC8088_profileManFreqTest(pCfg,pRegAddr,stopFreq);
		for(uint8_t i = 0;i<pllStartCnt;i++){
				pRegAddr->ANA.CFG01.WORD = rdata_cfg|(pll2StartVal[i]<<12);// printf("wdata_cfg[7] = 0x%08x \n",wdata_cfg[7]);
				HAL_RC8088_WrReg(pCfg, REG_ANA_CFG01, &pRegAddr->ANA.CFG01, 1);
				HW_Delay_ms(1);
				HAL_RC8088_ClrESR1Int(pCfg,&pRegAddr->INT);   //���֮ǰ״̬  //00000800
				HW_Delay_ms(1);
				reg_sta = HAL_RC8088_GetInt(pCfg,REG_ESR1); 
				if(((reg_sta &(0x1<<12))== 0)&&((reg_sta & (0x1<<13)) == 0))
				{
                    #if 0 //auto
                        pll2StopVal[pllStopCnt] = pll2StartVal[i];
                        pllStopCnt++;	
                    #endif
                    #if 1 //manual
                        pRegAddr->ANA.CFG02.WORD=pRegAddr->ANA.CFG02.WORD|(1<<6);HAL_RC8088_WrReg(pCfg, REG_ANA_CFG02, &pRegAddr->ANA.CFG02, 1); 
                        pRegAddr->ANA.CFG02.WORD=pRegAddr->ANA.CFG02.WORD|(3<<6);HAL_RC8088_WrReg(pCfg, REG_ANA_CFG02, &pRegAddr->ANA.CFG02, 1); 
                        reg_sta = HAL_RC8088_GetInt(pCfg,REG_ANA_STA3); 
                        pRegAddr->ANA.CFG02.WORD=pRegAddr->ANA.CFG02.WORD&0xFFFFFF3F;HAL_RC8088_WrReg(pCfg, REG_ANA_CFG02, &pRegAddr->ANA.CFG02, 1); 
                        reg_sta=(reg_sta>>10)&0x3FF;printf("PLL2:adc=%d \n",reg_sta);
                        if(reg_sta>157){//adc2:157=250mV
                            pll2StopVal[pllStopCnt] = pll2StartVal[i];
                            pllStopCnt++;	                
                        }
                    #endif							
				}
		}		
		HAL_RC8088_WaveStop(pCfg);
		if(pllStopCnt==0){ 
			pRegAddr->ANA.CFG01.WORD = rdata_cfg;
			printf("PLL2 %08X stop no band\n",rdata_cfg);
			rtn = RW_RTN_ERR;
		}else if(pllStopCnt==1){  
			pRegAddr->ANA.CFG01.WORD = rdata_cfg|(pll2StopVal[0]<<12); 
			rtn =	RW_OK;	
		}else{
			pRegAddr->ANA.CFG01.WORD = rdata_cfg|(pll2StopVal[1]<<12); 
			rtn =	RW_OK;			
		}
	}
    pRegAddr->ANA.CFG09.WORD=pRegAddr->ANA.CFG09.WORD&0xFFFFC7FF;
    HAL_RC8088_WrReg(pCfg, REG_ANA_CFG09, &pRegAddr->ANA.CFG09, 1);
	HAL_RC8088_WrReg(pCfg, REG_ANA_CFG01, &pRegAddr->ANA.CFG01, 1);	
	return rtn;
} 
RC8088_OperateStatus HAL_RC8088_CaliberVCO(RC8088_RWCfg_st *pCfg, RC8088_RegCfg_st *pRegAddr,uint32_t startFreq,uint32_t stopFreq)
{
    RC8088_RegDat_st u32Rdata;
     HAL_RC8088_RdReg(pCfg, REG_ANA_CFG02,&u32Rdata, 1);printf("ANA.CFG02=%08X\n",u32Rdata.DATA32);
//PLL1_Vcoband	
	if(PLL1_VCO_Calib(pCfg, pRegAddr)!=RW_OK){
		printf("PLL1 ERR\n");
		return RW_RTN_ERR;		
	}
    HAL_RC8088_RdReg(pCfg, REG_ANA_CFG02,&u32Rdata, 1);printf("ANA.CFG02=%08X\n",u32Rdata.DATA32);
//PLL2_Vcoband 
	if(PLL2_VCO_Calib(pCfg,pRegAddr,startFreq,stopFreq,0x065906F5)==RW_OK){//LK: 75.4G-80.2G band 0x0FFE0655   0x06F906F5   0x03F506F5
		printf("PLL2 LK OK=%08X\n",pRegAddr->ANA.CFG01.WORD);
        HAL_RC8088_RdReg(pCfg, REG_ANA_CFG02,&u32Rdata, 1);printf("ANA.CFG02=%08X\n",u32Rdata.DATA32);
		return RW_OK;
	}else 
	if(PLL2_VCO_Calib(pCfg,pRegAddr,startFreq,stopFreq,0x07FF06F2)==RW_OK){//HK:76.9G-85.7G band 0x0FFF0652
		printf("PLL2 HK OK=%08X\n",pRegAddr->ANA.CFG01.WORD);
		return RW_OK;
	}else{
		printf("PLL2 ERR\n");
		return RW_RTN_ERR;
	}
    #if 0
        pRegAddr->ANA.CFG01.WORD=0x06F926F5;//hk:0x07FF16F2; lk:0x06F926F5
        HAL_RC8088_WrReg(pCfg, &pRegAddr->ANA.CFG01, 1);	
        return RW_OK;
    #endif
   
   
}

/**
 * @Breif  : HAL_RC8088_RX_DC_Calib : RC8088 Caliber RX DC function
 *
 * @param  : *pCfg                 : pointer to RC8088 read and write configuration
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_LEN_ERR
 *                                 : RW_OK
 */
//0: 1mV, 7:15mV, 8:-1mV, F:-15mV,
static const uint32_t anaCfg17_BitBuf[16]={0x7,0x6,0x5,0x4,0x3,0x2,0x1,0x0,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF};
static const uint32_t anaCfg17_Buff[16]={0x77777777,0x66666666,0x55555555,0x44444444,0x33333333,0x22222222,0x11111111,0,0x88888888,0x99999999,0xAAAAAAAA,0xBBBBBBBB,0xCCCCCCCC,0xDDDDDDDD,0xEEEEEEEE,0xFFFFFFFF};
RC8088_OperateStatus HAL_RC8088_RX_DC_Calib(RC8088_RWCfg_st *pCfg, RC8088_RegCfg_st *pRegAddr){
	uint32_t oriRxGain=pRegAddr->ANA.CFG05.WORD;
    RC8088_CQ0_st stCQ0;
    static int16_t adcMean[16][8]={0};
    uint8_t minIdx[8]={0};
    uint16_t minAbsVal[8]={0};
    RC8088_RegDat_st u32Rdata;
    #if 1
//        rc8088_regCfg->OP_GATE.OP_GATE.WORD = 0xFFFFFFFF;
//        HAL_RC8088_WrReg(&RC8088_RW, &rc8088_regCfg->OP_GATE, 1);
        HAL_RC8088_WaveStart(pCfg);
    #endif
    pRegAddr->OP_GATE.OP_GATE.BIT.gate_prep = 0;
	HAL_RC8088_WrReg(pCfg, REG_OP_GATE, &pRegAddr->OP_GATE, 1);
    HAL_RC8088_RdReg(pCfg, REG_OP_GATE, &u32Rdata, 1);
    printf("OP_GATE:%08X\n",u32Rdata.DATA32);

//config ANACFG rxGain 
	pRegAddr->ANA.CFG05.BIT.Gainsta3=3; 
	pRegAddr->ANA.CFG05.BIT.Gainsta2=3; 
	pRegAddr->ANA.CFG05.BIT.Gainsta1=0; 
	HAL_RC8088_WrReg(pCfg, REG_ANA_CFG05, &pRegAddr->ANA.CFG05, 1);
//config profileMan
	pRegAddr->PROFILE_MAN.ProfileMan_CFG0.BIT.profile_man_vld=1;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG1.BIT.ramp_a_time=0x0190;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG1.BIT.ramp_a_inc=0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG2.BIT.ramp_b_time=0x0FA0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG2.BIT.ramp_b_inc=0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG3.BIT.ramp_c_time=0x0FA0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG3.BIT.ramp_c_inc=0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG4.BIT.startFreq=0x0112d794; //78G:0x0112d794
	pRegAddr->PROFILE_MAN.ProfileMan_CFG5.BIT.txEn=0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG5.BIT.adcRma=250;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG6.BIT.tx3Phase=0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG6.BIT.tx2Phase=0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG6.BIT.tx1Phase=0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG6.BIT.tx0Phase=0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG7.BIT.tx7Phase=0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG7.BIT.tx6Phase=0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG7.BIT.tx5Phase=0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG7.BIT.tx4Phase=0;	
	pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.loopNum=0;	
	pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.loopInf=0;	
	pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.pa_en_maskC=1;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.pa_en_maskB=1;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.pa_en_maskA=1;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.pll_acc_maskC=0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.pll_acc_maskB=0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.pll_acc_maskA=0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.ramp_sycn_maskC=0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.ramp_sycn_maskB=0;
	pRegAddr->PROFILE_MAN.ProfileMan_CFG8.BIT.ramp_sycn_maskA=1;
	HAL_RC8088_WrReg(pCfg, REG_PROF_MAN_CFG0, &pRegAddr->PROFILE_MAN.ProfileMan_CFG0, 9);
	
//config prep
	pRegAddr->PREP.PREP_CFG0.BIT.samp_pt=2048-1;	
	pRegAddr->PREP.PREP_CFG0.BIT.samp_pt_fac=0xFFF;	
	pRegAddr->PREP.PREP_CFG0.BIT.samp_pt_rsfb=11;//11:2048
	pRegAddr->PREP.PREP_CFG1.BIT.chirp_num=1-1;	
	pRegAddr->PREP.PREP_CFG1.BIT.chirp_rma=0;	
	pRegAddr->PREP.PREP_CFG1.BIT.pp_num=1-1;	
	pRegAddr->PREP.PREP_CFG1.BIT.rx_num=8-1;	
	pRegAddr->PREP.PREP_CFG2.BIT.adc_clk_mode=1;
	pRegAddr->PREP.PREP_CFG2.BIT.adc_dsize=2;
	pRegAddr->PREP.PREP_CFG2.BIT.adc_test_mode=0;
	pRegAddr->PREP.PREP_CFG2.BIT.adc_cat_mode=1;
	pRegAddr->PREP.PREP_CFG2.BIT.adc_lsb=0;
	pRegAddr->PREP.PREP_CFG2.BIT.down_fac=0;
	pRegAddr->PREP.PREP_CFG2.BIT.cic_sec=0;
	pRegAddr->PREP.PREP_CFG3.BIT.rx_antseq0=0;
	pRegAddr->PREP.PREP_CFG3.BIT.rx_antseq1=1;
	pRegAddr->PREP.PREP_CFG3.BIT.rx_antseq2=2;
	pRegAddr->PREP.PREP_CFG3.BIT.rx_antseq3=3;
	pRegAddr->PREP.PREP_CFG3.BIT.rx_antseq4=4;
	pRegAddr->PREP.PREP_CFG3.BIT.rx_antseq5=5;
	pRegAddr->PREP.PREP_CFG3.BIT.rx_antseq6=6;
	pRegAddr->PREP.PREP_CFG3.BIT.rx_antseq7=7;
	pRegAddr->PREP.PREP_CFG4.BIT.cq2_timing_limit=0x20;
	pRegAddr->PREP.PREP_CFG4.BIT.cq1_pt_fac=0x3F;
	pRegAddr->PREP.PREP_CFG4.BIT.cq1_pt_rsfb=5;
	pRegAddr->PREP.PREP_CFG5.BIT.cq_sec_num=0;
	pRegAddr->PREP.PREP_CFG5.BIT.cq_pt_num=32-1;
	pRegAddr->PREP.PREP_CFG5.BIT.cq12_ch_num=8-1;
	HAL_RC8088_WrReg(pCfg,REG_PREP_CFG0, &pRegAddr->PREP.PREP_CFG0, 6);
    #if 0
        memset((uint8_t *)BB_DBUF0_BASE,0,65536);
        memset((uint8_t *)BB_DBUF1_BASE,0,65536);
        HAL_RC8088_WrMem(pCfg, RC8088_PBUFF0_BASE, (RC8088_MemDat_st *)BB_DBUF0_BASE, (2048*8*2)>>4);//len:1=16Byte
        HAL_RC8088_WrMem(pCfg, RC8088_IBUFF0_CP, (RC8088_MemDat_st *)BB_DBUF0_BASE, 2048>>4);//len:1=16Byte
    #endif
//collect data
	for(uint32_t chirpNow=0;chirpNow<16;chirpNow++){
        pRegAddr->ANA.CFG17.WORD=anaCfg17_Buff[chirpNow]; HAL_RC8088_WrReg(pCfg, REG_ANA_CFG17, &pRegAddr->ANA.CFG17, 1);
        HAL_RC8088_WaveStart(pCfg);
		Cnt_Delay_ms(1);
//		HAL_RC8088_RdMem(pCfg, RC8088_PBUFF0_BASE, (RC8088_MemDat_st *)BB_DBUF0_BASE, (2048*8*2)>>4);
		HAL_RC8088_RdMem(pCfg, RC8088_IBUFF0_CQ0, (RC8088_MemDat_st *)&stCQ0, 64>>4);
        for(uint32_t rxNow=0;rxNow<8;rxNow++){
            adcMean[chirpNow][rxNow]=stCQ0.RX[rxNow].chX_dc;
        }
    }  
		#if 0 //printf adcData
			UART_Transmit_Bytes(&UART0, (uint8_t *)BB_DBUF0_BASE,2048*8*2);
			UART_Transmit_Bytes(&UART0, (uint8_t *)BB_DBUF1_BASE,64);
			while(1);
		#endif

//calc mean
    for(uint32_t rxNow=0;rxNow<8;rxNow++){
        minAbsVal[rxNow]=abs(adcMean[0][rxNow]);
        for(uint32_t chirpNow=1;chirpNow<16;chirpNow++){
            uint16_t absCurVal=abs(adcMean[chirpNow][rxNow]);
            if(absCurVal<minAbsVal[rxNow]){
                minAbsVal[rxNow]=absCurVal;
                minIdx[rxNow]=chirpNow;
            }
        }      
    }
    pRegAddr->ANA.CFG17.WORD=0;
    for(uint32_t rxNow=0;rxNow<8;rxNow++){
        pRegAddr->ANA.CFG17.WORD=pRegAddr->ANA.CFG17.WORD|anaCfg17_BitBuf[minIdx[rxNow]]<<(rxNow<<2);
    }
    HAL_RC8088_WrReg(pCfg, REG_ANA_CFG17, &pRegAddr->ANA.CFG17, 1);
//calib printf
    #if 0
        HAL_RC8088_WaveStart();
        Cnt_Delay_ms(1);
        HAL_RC8088_RdMem(pCfg, RC8088_PBUFF0_BASE, (RC8088_MemDat_st *)BB_DBUF0_BASE, (2048*8*2)>>4);
        HAL_RC8088_RdMem(pCfg, RC8088_IBUFF0_CQ0, (RC8088_MemDat_st *)&stCQ0, 64>>4);
        UART_Transmit_Bytes(&UART0, (uint8_t *)BB_DBUF0_BASE,2048*8*2);
        while(1);
    #endif
// reload rxGain
	pRegAddr->ANA.CFG05.WORD=oriRxGain;HAL_RC8088_WrReg(pCfg, REG_ANA_CFG05, &pRegAddr->ANA.CFG05, 1);
	pRegAddr->OP_GATE.OP_GATE.BIT.gate_prep = 1;
	HAL_RC8088_WrReg(pCfg, REG_OP_GATE, &pRegAddr->OP_GATE, 1);
	return RW_OK;
}
/**
 * @Breif  : HAL_RC8088_ADC_SYNC_CLK_Calib : RC8088 calibrate ADC SYNC and CLK function
 *
 * @param  : *pCfg                 : pointer to RC8088 read and write configuration
 * @param  : startFreq             : RC8088 start freq
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_LEN_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_ADC_SYNC_CLK_Calib(RC8088_RWCfg_st *pCfg, RC8088_RegCfg_st *pRegAddr,uint32_t startFreq){
	RC8088_OperateStatus rtn=RW_RTN_ERR;
	uint32_t oriAnaCfg13=pRegAddr->ANA.CFG13.WORD;
	RC8088_RegDat_st u32Rdata;
	uint32_t ctSyncDelay=0;
	pRegAddr->ANA.CFG13.WORD=pRegAddr->ANA.CFG13.WORD&0xF7FFFFFF;HAL_RC8088_WrReg(pCfg, REG_ANA_CFG13, &pRegAddr->ANA.CFG13, 1);
	pRegAddr->ANA.CFG13.WORD=pRegAddr->ANA.CFG13.WORD|0x08000000;HAL_RC8088_WrReg(pCfg, REG_ANA_CFG13, &pRegAddr->ANA.CFG13, 1);
	HAL_RC8088_profileManFreqTest(pCfg,pRegAddr,startFreq);
    Cnt_Delay_ms(1);
	HAL_RC8088_WaveStop(pCfg);
	HAL_RC8088_RdReg(pCfg, REG_ANA_STA2,&u32Rdata, 1); 
	uint32_t anaSta02=u32Rdata.DATA32>>24;
	for (int32_t i = 6; i >= 0; i--) {  
			uint32_t current_bit = (anaSta02 >> i) & 1;      //cur bit
			uint32_t previous_bit = ((anaSta02 >> (i + 1)) & 1);  //pre bit
			if (previous_bit == 0 && current_bit == 1) {  
				switch(i){
					case 0:
					case 1:
						ctSyncDelay=3;
						break;
					case 2:
					case 3:
						ctSyncDelay=2;
						break;
					case 4:
					case 5:
						ctSyncDelay=1;
						break;
					case 6:
						ctSyncDelay=0;
						break;					
				}
				rtn=RW_OK;
				break;
			}  
	} 
    if(rtn==RW_RTN_ERR){ //no rise  8'b11111100
        ctSyncDelay=0;
        rtn=RW_OK;
    }
	pRegAddr->ANA.CFG13.WORD=oriAnaCfg13&0xCFFFFFFF;HAL_RC8088_WrReg(pCfg, REG_ANA_CFG13, &pRegAddr->ANA.CFG13, 1);	
	pRegAddr->ANA.CFG13.WORD=pRegAddr->ANA.CFG13.WORD|(ctSyncDelay<<28);HAL_RC8088_WrReg(pCfg, REG_ANA_CFG13, &pRegAddr->ANA.CFG13, 1);
    
	#if 1
		printf("ANA_STA02=%08X\n",anaSta02);
		printf("ANA_CFG13=%08X,ctSyncDelay=%d\n",pRegAddr->ANA.CFG13.WORD,ctSyncDelay);
		if(rtn==RW_OK){
			printf("ADC SYNC CLK calib success\n");
		}else{
			printf("ADC SYNC CLK calib error\n");
		}
	#endif
	return rtn;
}
/**
 * @Breif  : HAL_RC8088_RC_Corner_Calib : RC8088 calibrate RC corner function
 *
 * @param  : *pCfg                 : pointer to RC8088 read and write configuration
 *
 * @Returns: RC8088_OperateStatus  : RW_IF_ERR
 *                                 : RW_LEN_ERR
 *                                 : RW_OK
 */
RC8088_OperateStatus HAL_RC8088_RC_Corner_Calib(RC8088_RWCfg_st *pCfg, RC8088_RegCfg_st *pRegAddr){
	RC8088_OperateStatus rtn=RW_RTN_ERR;
	uint32_t oriAnaCfg13 = pRegAddr->ANA.CFG13.WORD;
	RC8088_RegDat_st u32Rdata;
	uint32_t rtnData=0;
	pRegAddr->ANA.CFG13.WORD=pRegAddr->ANA.CFG13.WORD&0xFBFFFFFF;HAL_RC8088_WrReg(pCfg, REG_ANA_CFG13, &pRegAddr->ANA.CFG13, 1);	
	pRegAddr->ANA.CFG13.WORD=pRegAddr->ANA.CFG13.WORD|0x04000000;HAL_RC8088_WrReg(pCfg, REG_ANA_CFG13, &pRegAddr->ANA.CFG13, 1);	
	Cnt_Delay_ms(1);
	HAL_RC8088_RdReg(pCfg, REG_ANA_STA2,&u32Rdata, 1); 
	rtnData=(u32Rdata.DATA32>>16)&0xFF;
	rtnData=rtnData-0x3B;
	if(rtnData<0x02){                      
		rtn=RW_RTN_ERR;
	}else if(rtnData>=0x02&&rtnData<0x06){ //FFcorner,need calib
		printf("FFcorner,need calib\n");
		rtn=RW_OK;
	}else if(rtnData>=0x06&&rtnData<=0x0E){ //no need calib
		rtn=RW_OK;
	}else if(rtnData>0x0E&&rtnData<=0x13){ //SScorner,need calib
		printf("SScorner,need calib\n");
		rtn=RW_OK;
	}else if(rtnData>0x13){
		rtn=RW_RTN_ERR;
	}
	#if 1
		printf("ANA_STA02=0x%08X,rtnData=0x%02X,",u32Rdata.DATA32,rtnData);
		if(rtn==RW_OK){
			printf("RC corner calib success\n");
		}else{
			printf("RC corner calib error\n");
		}
	#endif	
	pRegAddr->ANA.CFG13.WORD=oriAnaCfg13;HAL_RC8088_WrReg(pCfg, REG_ANA_CFG13, &pRegAddr->ANA.CFG13, 1);	
	return rtn;
}
